September 30 - October 02, 2019 | INTERCONTINENTAL STEPHEN F. AUSTIN, Austin, TX
Conference Day One
Opening
8:00 am - 8:30 am Registration and Welcome Coffee
9:00 am - 9:10 am Chairperson's opening remarks
ZERO DEFECT STRATEGY
9:10 am - 9:50 am Keynote Opening Presentation: Zero Defect in Semiconductors - the Challenges and our Strategic Pushes for Superiority
- A reality check of defect immunity and challenges
- Navigating the “Road to Zero Defects” at ON Semiconductor
- A call for more collaborative endeavors towards zero defects assurance
Dr. Lieyi Sheng
Senior Member Technical Staff/ Quality & Reliability DirectorON Semiconductor
9:50 am - 10:30 am Speed Networking
Maximise your networking outcome at this event by participating in these fast-paced 1-to-1 meetings. Get to know the other attendees and exchange your business cards.
10:30 am - 11:00 am Coffee break and networking
11:00 am - 11:40 am Manufacturing challenges to drive Automotive Zero Defect in Advanced Nodes
• What is a defect?
• Lines of Defense: How to drive defect control backt to the tool
• Zero Defect Pareto: Focussing on hidden issues in yield and defect paretos
FAULT DETECTION AND PROCESS CONTROL
11:40 am - 12:20 pm Use Case; Tips for Zero Failures in Semiconductor Products
• Navigating along „Road to Zero Defects“
• How to proceed: Tips and Analysis
Dr. Lieyi Sheng
Senior Member Technical Staff/ Quality & Reliability DirectorON Semiconductor
12:20 pm - 1:00 pm Quality Management Practices used to achieve Zero Defect in Semiconductor-IP
• Quality is a foundation pillar to any product development. How can the robust methodologies like
Requirements traceability
Analysis of Designer and verification concerns help semiconductor IPs to reduce the number of critical defects within the design and development
• How can these directly contribute to developing a safe product to be used by the supply chain
1:00 pm - 2:30 pm Networking luncheon
2:30 pm - 3:10 pm Driving through Dppb: Optimal Test Strategies for Automotive Devices
• Test Methodologies in use today
• From plan to implementation - instrumentation, system, and production test package
development challenges
• Opportunities for improvement, near and further afield
3:10 pm - 3:50 pm Latent Reliability Defect Detection and Control
• Fab reliability defects
• Systematic defect reductions
• In-line Defect Part Average Testing
3:50 pm - 4:20 pm Networking and refreshment break
4:20 pm - 5:50 pm Integrated Workshop | Defects Screening Techniques at Product Sort
The workshop gives an insight in the Zero Defect Screening Techniques as failure analysis technology is not simply a means to investigate the failure causes and mechanisms of failed products. It is a vital and essential technology for quality and reliability improvement activities aimed at reducing failures in customer processes and the market to as close to zero as possible. The defect screening at product sort will help semiconductor manufacturers to adapt to the highest quality and reliability standards expected in the automotive market.
Dr. Lieyi Sheng
Senior Member Technical Staff/ Quality & Reliability DirectorON Semiconductor
5:50 pm - 6:00 pm Chairperson's closing remarks
6:10 pm - 9:30 pm Evening Get-Together
Join our evening Get-Together and take this opportunity to network and make new business contacts. Or just to relax and round off your first conference day.