Conference day 1
8:50 am - 9:00 am Opening by chairmanRiccardo Mariani - Chief Functional Safety Technologist Intel
8:00 am - 8:20 am Registration and welcome coffee
9:00 am - 9:40 am Panel Discussion | Welcome ISO 26262 part 11Riccardo Mariani - Chief Functional Safety Technologist Intel
Samir Camdzik - Systems Engineer, Texas Instruments
Chanthachith Souvanthong - Corporate Functional Safety Manager, ON Semiconductor
Yves Renard - Automotive BU Functional Safety Manager, ON Semiconductor, Belgium
Riccardo Vincelli - Director of the Functional Safety Competence Center, Renesas Electronics Europe GmbH
The ISO 26262 standard for functional safety in automotive E/E systems so far did not provide clear instructions for semiconductor companies. The freshly added part 11 is dedicated only to the semiconductor industry and aims d closing big gaps. Due to its novelty, part 11 offers quiet a lot of discussion potential on how to interpret and apply it. This panel will address the most important issues.
• The great achievement – Learn to read ISO 26262 part 11
• Application challenges and how to best overcome them
• FMEDA and FTA – Should they stay or should they go now?
Samir CamdzikSystems Engineer
Chanthachith SouvanthongCorporate Functional Safety Manager
Yves RenardAutomotive BU Functional Safety Manager
ON Semiconductor, Belgium
Riccardo VincelliDirector of the Functional Safety Competence Center
Renesas Electronics Europe GmbH
9:40 am - 10:20 am Match & Win
10:10 am - 10:40 am Coffee break
10:40 am - 11:20 am Scene Setting | From Semiconductor Components to ISO 26262 Compliant Functionally Safe SystemsSamir Camdzik - Systems Engineer, Texas Instruments
Bharat Rajaram - Director of Functional Safety, Texas Instruments
This presentation will begin by describing how to apply the ISO 26262-11:2018 standard for both semiconductor components developed as part of a compliant item as well as an SEooC. The presenters will then discuss
• How (during Functional Safety Analysis), the semiconductor component is divided into parts, subparts and elementary subparts
• What (and why), is the necessary and sufficient analysis technique?
• HW failure modes and how they relate to both HW faults and errors
• Failure modes, fault models and techniques to distribute base fail rates will be outlined
A case study that tackles mixed-signal fault injection and failure mode distributions will be presented. Finally, a method to leverage component safety analysis to the design and production of functionally safe systems is described.
Samir CamdzikSystems Engineer
Bharat RajaramDirector of Functional Safety
11:20 am - 12:00 pm Flow for Measuring Diagnostic Coverage in IP Blocks to Reach Target ASILsShivakumar Chonnad - Senior Staff Engineer - IP Quality and Functional Safety, Synopsys
Shrenik Metha - Program Management Director, Synopsys
Diagnostic coverage is a key metric to achieve target ASILs for safety-critical systems. This
session describes a case study and best practices to determine the required diagnostic coverage
during a fault injection campaign in an IP core. We will detail the methodology and fault injection
• Steps in a fault campaign flow- Input data required for fault injection
• Analysis of the output data for convergence- Issues, challenges, and recommendations
Shivakumar ChonnadSenior Staff Engineer - IP Quality and Functional Safety
Shrenik MethaProgram Management Director
12:00 pm - 12:40 pm Application Specific Safeness Analysis for SemiconductorsBalaji Venu - Staff Research Engineer, ARM
Reliability estimation is critical for the safety analysis of cyber-physical systems (e.g. Automotive). With increasing system complexity, meeting functional safety requirements using existing methods is a challenge. This presentation will describe
• An analytical methodology for reliability estimation
• Show results of a practical example on the microarchitecture for Arm CPUs
• This application-specific, fine-grained methodology will enable a reliability aware design process that helps meet functional safety requirements by promoting collaboration between OEMs, Tier1s and Silicon Partners.
Balaji VenuStaff Research Engineer
12:40 pm - 1:40 pm Network luncheon
1:40 pm - 2:20 pm ISO-26262 for ASIC engineers, introductionJamil Mazzawi - Founder and CEO - Functional Safety, Optima Design Automation
In this presentation we give an introduction for ISO-26262 requirements from semiconductor and IP vendors. The presentation is in the language of the average ASIC design and verification engineers. Then we discuss how Optima’s tools address these requirements.
Jamil MazzawiFounder and CEO - Functional Safety
Optima Design Automation
2:20 pm - 3:00 pm A systematic extraction of failure modes for analogue cricuitsRenaud Gillon - Program Manager ON Semiconductor
A method is proposed allowing to automatically identify the failure modes of an analogue circuit based on fault-injection simulations. Based on the similarity of the induced faulty behaviors, a clustering is realized and one fault per group is elected as representative of the failure mode.
Modal fault models are then extracted using the wrapper approach.
• Analogue circuits
• Abstract fault models
Renaud GillonProgram Manager
3:00 pm - 3:40 pm Challenges and opportunities for automotive semiconductor design and verification methodologiesAlessandra Nardi - Software Engineering Group Director, Cadence Design Systems, USA
Art Schaldenbrand - Senior Product Manager, Cadence Design Systems
As automotive applications grow in complexity and size, the challenges to support the development of safety critical components are increasing and so are the opportunities. There is a significant need for new design and verification methodologies to fulfill automotive requirements as an integral part of the EDA (Electronic Design Automation) flow for digital, analog, and mixed-signal semiconductors.
• FMEDA meets EDA
• Opportunities for safety optimization
• Challenges of consistency and standardization
Alessandra NardiSoftware Engineering Group Director
Cadence Design Systems, USA
Art SchaldenbrandSenior Product Manager
Cadence Design Systems
3:40 pm - 4:10 pm Refreshment break and networking
4:10 pm - 4:50 pm Panel Discussion | Expectations by Tier 1 & OEM – How a successful corporation could look likeBharat Rajaram - Director of Functional Safety Texas Instruments
Dr. Rafael Zalman - Senior Principal Functional Safety Development, Infineon Technologies AG
Dr. Christian Kehl - Automotive Electronics, Engineering Sensors Inertial: Acceleration, Robert Bosch GmbH
Panos Gnafakis - Lead Embedded Software Design SME - Advanced Electronics, Jaguar Land Rover
This panel discussion serves as an exchange of ideas between semiconductor companies, Tier 1 and OEM in order to discuss challenges and successes in their corporation. Ideas of improvement will be discussed and different views on the inter-work will be given.
Bharat RajaramDirector of Functional Safety
Dr. Rafael ZalmanSenior Principal Functional Safety Development
Infineon Technologies AG
Dr. Christian KehlAutomotive Electronics, Engineering Sensors Inertial: Acceleration
Robert Bosch GmbH
Panos GnafakisLead Embedded Software Design SME - Advanced Electronics
Jaguar Land Rover
4:50 pm - 5:30 pm Functional safety from a system power supply point of viewOle-Kristian Skroppa - Senior Staff Application Engineer Safety System Power Supplies Infineon Technologies AG, Germany
Power Management Integrated Circuits (PMIC) manage the power requirements of the host system. The PMIC market faces strong trends towards a growing demand for energy-efficient battery-powered devices, as well as increased sales in the automotive sector. This presentation
will cover the main functional safety aspects of PMIC.
• Interaction between Safety PMIC and Safety MCU
• Safety vs. availability
• Fail Silent vs. Fail Operational
Ole-Kristian SkroppaSenior Staff Application Engineer Safety System Power Supplies
Infineon Technologies AG, Germany