June 11 - 14, 2019 | Sheraton Ann Arbor Hotel, Ann Arbor, MI

Agenda Day 2

8:30 am - 9:00 am Registration and welcome coffee

9:00 am - 9:10 am Opening remarks by Chairman

Riccardo Mariani, Chief Functional, Safety Technologist, Intel

APPLICATION OF REAL WORLD EXAMPLES

9:10 am - 9:50 am Practical Application of ISO 26262 Part 11

Practical application of ISO26262 part 11
Part 11 represents an adaptation of ISO 26262 specifically to semiconductor devices to facilitate
the application of the standard’s requirements. However, semiconductor developers must address
several key considerations in order to successfully apply Part 11 to their devices. This talk will
address some of these considerations by way of example application of Part 11 to Intel’s products.
Topics to be discussed include:
• Relation of component safety analysis to system analysis
• Standardizing functional safety support for easing IP integration
• Dealing with analog/mixed-signal and multi-core components
• Dealing practically with DFA
Gustavo Espinosa, Senior Principal Engineer, Lead Architect for Functional Safety, Intel Corporation
Gustavo Espinosa, Senior Principal Engineer, Lead Architect for Functional Safety, Intel Corporation
Gustavo Espinosa, Senior Principal Engineer Lead Architect for Functional Safety at Intel

Gustavo Espinosa

Senior Principal Engineer Lead Architect for Functional Safety
Intel

Moderator:
Rahul Gulati, SoC Functional Safety Architect, Qualcomm

Panelists:
Nestor Grace, Electrical Architect & Vehicle Systems Engineer, Faraday Future
Charles Gu, Autonomous Vehicle System Safety Engineer, General Motors Company
Scott Wendling, Technical Manager - Safety and Software, Halla Mechatronics
Rahul Gulati, SoC Functional Safety Architect at Qualcomm

Rahul Gulati

SoC Functional Safety Architect
Qualcomm

Charles Gu, Autonomous Vehicle System Safety Engineer at General Motors

Charles Gu

Autonomous Vehicle System Safety Engineer
General Motors

Gurmit Banvait, Senior Safety Engineer - Autonomous Vehicles at General Motors at General Motors

Gurmit Banvait

Senior Safety Engineer - Autonomous Vehicles at General Motors
General Motors

Scott Wendling, Technical Manager - Safety and Software, at Halla Mechatronics

Scott Wendling

Technical Manager - Safety and Software,
Halla Mechatronics

10:30 am - 11:00 am Refreshment break and networking

BASE FAILURE RATE FOR SEMICONDUCTORS

11:00 am - 11:40 am Safety analysis - How to better integrate a FMEDA in the Tier1 system level

Safety analysis - How to better integrate a FMEDA in the Tier1 system level
• Understanding what needs to be done to integrate it more easily
• Changes that need to be made to accelerate this process
• Finding the right level of abstraction
• Looking into the future
Lisa Clark, Functional Safety Manager, Veoneer
Lisa Clark, Functional Safety Manager at Veoneer

Lisa Clark

Functional Safety Manager
Veoneer

This presentation will identify new failure risks in the advanced semiconductors that are needed
in ADAS and autonomous systems.
• The immense processing power needed for autonomous vehicles requires advanced, next
generation ICs. New/next generations E/E technologies and materials have new or different
failure behaviors that cannot be predicted using the historical, failure rates from previous
generation of generic E/E tech that are assumed to be life-long constants
• A more effective, alternate approach that has proven to be highly effective, especially for
new technologies
• The lack a field history, is to perform Reliability Physics Analysis (RPA) to identify design and
application specific failure mechanism susceptibilities and how failure risks increase as
electronics age. RPA involves performing dynamic multi-physic load/stress analysis combined
with durability simulations using failure mechanism models derived from Physics of Failure
(PoF) research performed in a Computer Aided Engineering (CAE) Environment
• RPA/PoF methods are defined and recognized as a way to identify failure risks in the 2018
update of ISO-26262-2018. A joint SAE Automotive and Aerospace standard SAE J3168
“Reliability Physics Analysis of Electronic Equipment, Modules and Components” is now in
development to standardize the approach and define best practices
James McLeish, Automotive Technical Expert & Senior Member of Technical Staff Senior
Reliability/Test Engineer, DfR Solutions - Southeast Michigan Automotive Office
Keith Hodgson, Subject Matter Expert for E/E Reliability-Durability, Ford Motor Co
James McLeish, Automotive Technical Expert & Senior Member of Technical Staff at DfR Solutions - Southeast Michigan Automotive Office

James McLeish

Automotive Technical Expert & Senior Member of Technical Staff
DfR Solutions - Southeast Michigan Automotive Office

Keith Hodgson, Senior Reliability/Test Engineer - Subject Matter Expert for E/E Reliability-Durability at Ford Motor Co. USA

Keith Hodgson

Senior Reliability/Test Engineer - Subject Matter Expert for E/E Reliability-Durability
Ford Motor Co. USA

12:20 pm - 12:50 pm Achieving a Traceable Design and IP Methodology for ISO 26262 Compliance

While solutions exist for traceability for requirements, design and verification, these solutions are often not connected and error prone when information attempts to be shared. This presentation will discuss:
• How to automate traceability from requirements through design to verification
• Automating the documentation of the traceabiity

Michael Munsey, Vice President Corporate Strategy and Business Development, Methodics Inc.
Michael Munsey, Vice President Business Development and Strategic Accounts at Methodics, Inc. USA

Michael Munsey

Vice President Business Development and Strategic Accounts
Methodics, Inc. USA

12:50 pm - 1:50 pm Networking luncheon

ADAS & SEMICONDUCTORS

Moderator:
Riccardo Mariani, Chief Functional, Safety Technologist, Intel

Panelists:
Michael Ryzyi, Principal Engineer Functional Safety, Lear
Scott Wendling, Technical Manager - Safety and Software, Halla Mechatronics
Mauro Pipponzi, Intel Functional Safety Tools, Flows and Methodologies Architect at Intel Corporation

Mauro Pipponzi

Intel Functional Safety Tools, Flows and Methodologies Architect
Intel Corporation

Scott Wendling, Technical Manager - Safety and Software, at Halla Mechatronics

Scott Wendling

Technical Manager - Safety and Software,
Halla Mechatronics

Michael Ryzyi, Principal Engineer Functional Safety at Lear, USA

Michael Ryzyi

Principal Engineer Functional Safety
Lear, USA

Mauro Pipponzi, Intel Functional Safety Tools, Flows and Methodologies Architect at Intel Corporation

Mauro Pipponzi

Intel Functional Safety Tools, Flows and Methodologies Architect
Intel Corporation

2:30 pm - 3:10 pm Autonomous driving and its impact on automotive safety development

Traditional tiered supply structure in automotive development is facing challenges to produce
safe autonomous vehicles. New models are needed to ensure that expertise is leveraged
wherever it exists in the supply chain. This presentation will look deeper at how the integration
of DNNs (Deep Neural Networks) for autonomous driving is impacting traditional development
approaches and how OEMs, Tier1s, and Tier2s can work together to build a safer product.
• Role of DNNs in autonomous driving
• Traditional development approach
• OEM/Tier1/Tier2 collaboration challenges
• Performance and safety optimization for complex hardware
• DNN Training
• Adaptation of trained DNNs for new vehicles
• V&V of DNNs
• Future Challenges
Frank Noha, Safety Specialist, NVIDIA
Frank Noha, Safety Specialist at NVIDIA, USA

Frank Noha

Safety Specialist
NVIDIA, USA

3:10 pm - 3:40 pm Refreshment break and networking

3:40 pm - 4:20 pm Link Safety & cyber security

Safety considerations from Cyber security of view
• Similarities and differences between Safety and Security
• Challenges to overcome in EE architectures and components
Chanthachith Souvanthong, Corporate Functional, Safety Manager, ON Semiconductor
Chanthachith Souvanthong, Corporate Functional Safety Manager at ON Semiconductor

Chanthachith Souvanthong

Corporate Functional Safety Manager
ON Semiconductor

4:20 pm - 4:45 pm Lessons Learned from Fault Injection of Complex System-on-Chip Interconnects

Describes lessons learned and methods to validate the presence and functionality of SoC safety mechanisms using fault injection. Describes best practices for:
·Fault simulator setup and integration with interconnect verification environments and testbenches
·Selecting insertion and observation points in RTL and netlists
·Reporting and tracing results back to the design implementation

Kurt Shuler, Vice President of Marketing & Functional Safety Manager, Arteris IP, USA
Diego Botero ,Corporate Applications Engineer & Functional Engineer, Arteris IP

Kurt Shuler, Vice President of Marketing at Arteris, Inc.

Kurt Shuler

Vice President of Marketing
Arteris, Inc.

Diego Botero, Corporate Applications Engineer & Functional Engineer at Arteris IP

Diego Botero

Corporate Applications Engineer & Functional Engineer
Arteris IP

4:45 pm - 5:25 pm Design Tools Classification and Qualification in a Safety Related Environment

Design tools classification and qualification in a safety related environment
• This presentation will focus on a review of:
• The classification
• Qualification
• Certification requirements on design tools
• As well as of the costs it implies and
• How to deal with them
Mauro Pipponzi, Intel Functional Safety Tools, Flows and Methodologies Architect, Intel Corporation
Mauro Pipponzi, Intel Functional Safety Tools, Flows and Methodologies Architect at Intel Corporation

Mauro Pipponzi

Intel Functional Safety Tools, Flows and Methodologies Architect
Intel Corporation

5:25 pm - 5:35 pm Closing remarks by Chairman

Riccardo Mariani, Chief Functional, Safety Technologist, Intel

5:35 pm - 5:35 pm End of conference see you in 2020